1. Field of the Invention
The present invention relates to a method for the operational check of a programmable logic array in which input lines, intersecting product term lines and ground lines are combined into an AND plane, in which the product term lines, in addition, are combined with intersecting output lines and ground lines into an OR plane, and in which switching transistors are provided at selected points of intersection of both planes, whereby, first, a sequence of bit patterns is applied to the input lines and, as a function of the switching transistor disposed in at least one plane, output bit patterns are derived over the output lines, which output patterns are investigated as to deviation from a reference result.
2. Description of the Prior Art
A programmable logic array (PLA) of the type set forth above can be derived, for example, from the German Letters Pat. No. 25 19 078, which corresponds to U.S. Pat. No. 4,041,459, which is fully incorporated herein by this reference. As can be determined from the article of T. W. Williams and E. B. Eichelberger entitled "Random Patterns Within A Structured Sequential Logic Design", Digest of Papers, 1977 Semiconductor Test Symposium, pp. 19-27, particularly pp. 24 and 25 and FIG. 9, also fully incorporated herein by this reference, an operational check of a PLA is executed in such a manner that a multitude of bit patterns are applied to its inputs and the output bit patterns occurring at the outputs are. evaluated in terms of potential deviations from reference patterns. However, given the use of pseudo-random patterns which can be generated by simple test data generators, the disadvantage occurs that, given larger PLA's with numerous inputs and outputs, only approximately 60% of the possibly existing circuit faults can be detected given the use of approximately 1,000 bit patterns. In order to detect all faults, a test data generator is required which, as a function of the PLA circuit to be tested, emits specially selected bit patterns. Thereby, however, the selection of the bit patterns is involved and time consuming and the test data generators required for this purpose are very complex.